The present disclosure relates to field-effect transistor devices and more particularly, to techniques for fabricating a stacked planar field-effect transistor device.
In its basic form, a field-effect transistor (“FET”) includes a source region, a drain region and a channel between the source and drain regions. A gate regulates electron flow through the channel between the source and drain regions.
Gate all-around or double gate lamellar FETs may enable density scaling beyond current planar complementary metal-oxide-semiconductor (“CMOS”) or fin FET (“FinFET”) technology. There are, however, notable challenges related to fabrication and structure of gate all-around or double gate lamellar FETs.